Gate driving circuit and display device

ABSTRACT

Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register. In the gate driving circuit of a cascade structure provided by the present disclosure, there are fewer cascade signal lines, thereby saving space, further implementing the narrow bezel of a display device; in addition, for the gate driving circuit of a cascade structure provided by the present disclosure, the signal provided by an external circuit board can be more flexible, even if a display product is manufactured, the pulse width of a clock signal can be adjusted by means of the external circuit board, thereby adjusting the high-level width of a gate signal output by a gate signal output end, and the flexibility is high.

CROSS REFERENCE TO RELATED APPLICATIONS

The disclosure is a national phase entry under 35 U.S.C. § 371 of International Application No. PCT/CN2021/075127, filed on Feb. 3, 2021, which claims priority to Chinese Patent Application No. 202010129236.0, entitled “GATE DRIVING CIRCUIT AND DISPLAY DEVICE”, filed to China National Intellectual Property Administration on Feb. 28, 2020, the entire contents of which are incorporated herein by reference.

FIELD

The disclosure relates to the technical field of display, in particular to a gate driving circuit and a display device.

BACKGROUND

With the rapid development of display technology, a display shows a development trend of high integration and low cost. A GOA (gate driver on array) technology integrates a TFT (thin film transistor) gate switching circuit on an array substrate of a display panel to achieve scanning drive of the display panel, so as to eliminate wiring spaces of a bonding region and a fan-out region of a gate integrated circuit (IC). The product cost can be reduced in terms of the material cost and a manufacturing process, and a beautiful design of symmetrical and narrow bezels on two sides can be realized on the display panel; moreover, the integration process can further eliminate the bonding process in a direction of a gate scanning line, so as to improve productivity and yield.

SUMMARY

An embodiment of the disclosure provides a gate driving circuit, including a plurality of cascaded shift registers, wherein each shift register includes an input signal terminal, a reset signal terminal, an output control terminal and a gate signal output terminal; the gate signal output terminals are electrically connected to gate lines of a display panel in a one-to-one corresponding mode; in every five adjacent shift registers, an output control terminal of a first shift register among the every five adjacent shift registers is electrically connected to an input signal terminal of a fifth shift register among the every five adjacent shift registers; and in every six adjacent shift registers, an output control terminal of a sixth shift register among the every six adjacent shift registers is electrically connected to the reset signal terminal of the first shift register among the every six adjacent shift registers.

In one possible implementation, the gate driving circuit provided by the embodiment of the disclosure, includes 10 clock signal lines, wherein each shift register further includes a clock signal terminal; the clock signal terminal of the (10k−9)th shift register is electrically connected to the first clock signal line, the clock signal terminal of the (10k−8)th shift register is electrically connected to the second clock signal line, the clock signal terminal of the (10k−7)th shift register is electrically connected to the third clock signal line, the clock signal terminal of the (10k−6)th shift register is electrically connected to the fourth clock signal line, the clock signal terminal of the (10k−5)th shift register is electrically connected to the fifth clock signal line, the clock signal terminal of the (10k−4)th shift register is electrically connected to the sixth clock signal line, the clock signal terminal of the (10k−3)th shift register is electrically connected to the seventh clock signal line, the clock signal terminal of the (10k−2)th shift register is electrically connected to the eighth clock signal line, the clock signal terminal of the (10k−1)th shift register is electrically connected to the ninth clock signal line, and the clock signal terminal of the (10k)th shift register is electrically connected to the tenth clock signal line; and k is a positive integer.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, a clock signal duty cycle of each clock signal line is approximately 40%.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, each shift register includes: an input circuit, a reset circuit, a control circuit, a first output circuit, a second output circuit and a frame start circuit. The input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal; the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal; the control circuit is configured to provide the signal of the first reference signal terminal to a second node in response to the signal input by the input signal terminal, control the potentials of the first node and the second node in response to a signal input by a control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the second node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the second node; the first output circuit is configured to provide a signal of the clock signal terminal to the gate signal output terminal in response to the potential of the first node; the second output circuit is configured to provide the signal of the clock signal terminal to the output control terminal in response to the potential of the first node; and the frame start circuit is configured to provide the signal of the first reference signal terminal to the first node in response to a signal input by a frame start signal terminal.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the input circuit includes a first switching transistor; and a gate and a first electrode of the first switching transistor are electrically connected to the input signal terminal, and a second electrode of the first switching transistor is electrically connected to the first node.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the reset circuit includes: a second switching transistor; and a gate of the second switching transistor is electrically connected to the reset signal terminal, a first electrode of the second switching transistor is electrically connected to the first node, and a second electrode of the second switching transistor is electrically connected to the first reference signal terminal.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the control circuit includes: a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor and a tenth switching transistor. A gate of the third switching transistor is electrically connected to the input signal terminal, a first electrode of the third switching transistor is electrically connected to the second node, and a second electrode of the third switching transistor is electrically connected to the first reference signal terminal. A gate of the fourth switching transistor is electrically connected to the second node, a first electrode of the fourth switching transistor is electrically connected to the first node, and a second electrode of the fourth switching transistor is electrically connected to the first reference signal terminal. A gate of the fifth switching transistor is electrically connected to the second node, a first electrode of the fifth switching transistor is electrically connected to the gate signal output terminal, and a second electrode of the fifth switching transistor is electrically connected to the second reference signal terminal. A gate and a first electrode of the sixth switching transistor are electrically connected to the control signal terminal, and a second electrode of the sixth switching transistor is electrically connected to a first electrode of the eighth switching transistor and a gate of the seventh switching transistor respectively. A first electrode of the seventh switching transistor is electrically connected to the control signal terminal, and a second electrode of the seventh switching transistor is electrically connected to the second node. A gate of the eighth switching transistor is electrically connected to the first node, and a second electrode of the eighth switching transistor is electrically connected to the first reference signal terminal. A gate of the ninth switching transistor is electrically connected to the first node, a first electrode of the ninth switching transistor is electrically connected to the second node, and a second electrode of the ninth switching transistor is electrically connected to the first reference signal terminal. A gate of the tenth switching transistor is electrically connected to the second node, a first electrode of the tenth switching transistor is electrically connected to the output control terminal, and a second electrode of the tenth switching transistor is electrically connected to the first reference signal terminal.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, two control circuits are provided and electrically connected to different control signal terminals respectively, and the two control signal terminals alternately input valid control signals.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the first output circuit includes: an eleventh switching transistor and a capacitor. A gate of the eleventh switching transistor is electrically connected to the first node, a first electrode of the eleventh switching transistor is electrically connected to the clock signal terminal, and a second electrode of the eleventh switching transistor is electrically connected to the gate signal output terminal; and the capacitor is connected between the gate and the second electrode of the eleventh switching transistor.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the second output circuit includes: a twelfth switching transistor; and a gate of the twelfth switching transistor is electrically connected to the first node, a first electrode of the twelfth switching transistor is electrically connected to the clock signal terminal, and a second electrode of the twelfth switching transistor is electrically connected to the output control terminal.

In one possible implementation, in the gate driving circuit provided by the embodiment of the disclosure, the frame start circuit includes: a thirteenth switching transistor; and a gate of the thirteenth switching transistor is electrically connected to the frame start signal terminal, a first electrode of the thirteenth switching transistor is electrically connected to the first node, and a second electrode of the thirteenth switching transistor is electrically connected to the first reference signal terminal.

Correspondingly, an embodiment of the disclosure further provides a display device, including the gate driving circuit provided by the embodiment of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a gate driving circuit provided in the related art.

FIG. 2 is a schematic timing chart for the gate driving circuit shown in FIG. 1 .

FIG. 3 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.

FIG. 4 is a schematic timing chart for the gate driving circuit shown in FIG. 3 .

FIG. 5 is a specific schematic structural diagram of a shift register in which all transistors are N-type transistors provided by an embodiment of the disclosure.

DETAILED DESCRIPTION

The specific implementations of a gate driving circuit and a display device provided by the embodiments of the disclosure will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a gate driving circuit provided in the related art, which adopts 10CLK design. The gate driving circuit includes a plurality of cascaded shift registers (GOA(n−4), GOA(n−3) GOA(n+4), GOA(n+5)), each shift register includes an input signal terminal IN, a reset signal terminal RS, an output control terminal OC and a gate signal output terminal G-O. The gate signal output terminals G-O are electrically connected to gate lines of a display panel in a one-to-one correspondence. In every six adjacent shift registers, such as six adjacent shift registers from GOAn to GOA(n+5), the output control terminal OC of the first shift register GOAn is electrically connected to the input signal terminal IN of the sixth shift register GOA(n+5). For six adjacent shift registers from GOA(n−1) to GOA(n+4), the output control terminal OC of the first shift register GOA(n−1) is electrically connected to the input signal terminal IN of the sixth shift register GOA(n+4), and so on.

In every seven adjacent shift registers, such as seven adjacent shift registers from GOAn to GOA(n+6), the output control terminal OC of the seventh shift register GOA(n+6) is electrically connected to the reset signal terminal RS of the first shift register GOAn; while for seven adjacent shift registers from GOA(n−1) to GOA(n+5), the output control terminal OC of the seventh shift register GOA(n+5) is electrically connected to the reset signal terminal RS of the first shift register GOA(n−1); and so on.

A cascade structure shown in FIG. 1 resets a first node PU in a GOA circuit by delaying the time of 1 row, so as to reverse discharge a gate line to a CLK signal through a switching transistor electrically connected to a CLK. As shown in FIG. 2 , FIG. 2 is an input and output timing chart of each shift register in the gate driving circuit shown in FIG. 1 . It can be seen that in the cascade structure design of FIG. 1 , the time of a high pulse signal and a low pulse signal of the CLK accounts for half respectively, the clock signal duty cycle only is 50%, the flexibility of an external circuit board to input a clock signal to a clock signal line is poor, and there are many cascade signal lines in the cascade structures shown in FIG. 1 , which is not conductive to saving space to further realize a narrow bezel.

In view of this, the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 3 , includes a plurality of cascaded shift registers ( . . . GOA(n−4), GOA(n−3) . . . GOA(n+4), GOA(n+5) . . . ), each shift register includes an input signal terminal IN, a reset signal terminal RS, an output control terminal OC and a gate signal output terminal G-O. The respective gate signal output terminals G-O are electrically connected to gate lines of a display panel in a one-to-one corresponding mode.

In every five adjacent shift registers, such as five adjacent shift registers from GOAn to GOA(n+4), the output control terminal OC of the first shift register GOAn is electrically connected to the input signal terminal IN of the fifth shift register GOA(n+4); while for five adjacent shift registers from GOA(n−1) to GOA(n+3), the output control terminal OC of the first shift register GOA(n−1) is electrically connected to the input signal terminal IN of the fifth shift register GOA(n+3), and so on.

In every six adjacent shift registers, such as six adjacent shift registers from GOAn to GOA(n+5), the output control terminal OC of the sixth shift register GOA(n+5) is electrically connected to the reset signal terminal RS of the first shift register GOAn; for six adjacent shift registers from GOA(n−1) to GOA(n+4), the output control terminal OC of the sixth shift register GOA(n+4) is electrically connected to the reset signal terminal RS of the first shift register GOA(n−1); and so on.

In the gate driving circuit provided by the embodiment of the disclosure, in every five adjacent shift registers, the output control terminal of the first shift register is electrically connected to the input signal terminal of the fifth shift register; and in every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register, so that there are fewer cascade signal lines in the gate driving circuit of the cascade structure, thereby saving space, and further implementing the narrow bezel of a display device. In addition, for the gate driving circuit of the cascade structure provided by the disclosure, the signal provided by the external circuit board can be more flexible, even if a display product is manufactured, a pulse width of a clock signal can be adjusted by means of the external circuit board, thereby adjusting a high-level width of a gate signal output by the gate signal output terminal, and the flexibility is high.

In the specific implementation, the gate driving circuit provided by the embodiment of the disclosure, as illustrated in FIG. 3 , includes 10 clock signal lines (CLK1, CLK2, CLK3 . . . CLK10), and each shift register further includes a clock signal terminal CLK.

The clock signal terminal of the (10k−9)th shift register is electrically connected to the first clock signal line, for example, clock signal terminals of first, 11th, 21th shift registers are electrically connected to the first clock signal line CLK1 respectively.

The clock signal terminal of the (10k−8)th shift register is electrically connected to the second clock signal line, for example, clock signal terminals of second, 12th, 22th shift registers are electrically connected to the second clock signal line CLK2 respectively.

The clock signal terminal of a (10k−7)th shift register is electrically connected to the third clock signal line, for example, clock signal terminals of third, 13th, 23th shift registers are electrically connected to the third clock signal line CLK3 respectively.

The clock signal terminal of a (10k−6)th shift register is electrically connected to the fourth clock signal line, for example, clock signal terminals of fourth, 14th, 24th . . . shift registers are electrically connected to the fourth clock signal line CLK4 respectively.

The clock signal terminal of the (10k−5)th shift register is electrically connected to the fifth clock signal line, for example, clock signal terminals of fifth, 15th, 25th . . . shift registers are electrically connected to the fifth clock signal line CLK5 respectively.

The clock signal terminal of the (10k−4)th shift register is electrically connected to the sixth clock signal line, for example, clock signal terminals of sixth, 16th, 26th . . . shift registers are electrically connected to the sixth clock signal line CLK6 respectively.

The clock signal terminal of the (10k−3)th shift register is electrically connected to the seventh clock signal line, for example, clock signal terminals of seventh, 17th, 27th . . . shift registers are electrically connected to the seventh clock signal line CLK7 respectively.

The clock signal terminal of the (10k−2)th shift register is electrically connected to the eighth clock signal line, for example, clock signal terminals of eighth, 18th, 28th . . . shift registers are electrically connected to the eighth clock signal line CLK8 respectively.

The clock signal terminal of the (10k−1)th shift register is electrically connected to the ninth clock signal line, for example, clock signal terminals of ninth, 19th, 29th . . . shift registers are electrically connected to the ninth clock signal line CLK9 respectively.

The clock signal terminal of the (10k)th shift register is electrically connected to the tenth clock signal line, for example, clock signal terminals of tenth, 20th, 30th . . . shift registers are electrically connected to the tenth clock signal line CLK10.

Here, k is a positive integer.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 4 , which is an input and output timing chart of each shift register in the gate driving circuit shown in FIG. 3 . Here a clock signal duty cycle of each clock signal line is about 40%. In this way, the cascade structure provided by the embodiment of the disclosure is adopted, so that the clock signal duty cycle of each clock signal line may be about 40%, the signal provided by the external circuit board can be more flexible, even if the display product is manufactured, the pulse width of the clock signal can be adjusted by means of the external circuit board, thereby adjusting the high-level width of the gate signal output by the gate signal output terminal, and the flexibility is high.

It should be noted that the clock signal duty cycle of each clock signal line may also be slightly higher than 40% or slightly lower than 40%, which is designed according to actual needs.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , each shift register may include: an input circuit 1, a reset circuit 2, a control circuit, a first output circuit 4, a second output circuit 5 and a frame start circuit 6. In order to avoid the problem of characteristic offset or even damage of a switching transistor caused by long-time direct-current bias of a switching transistor of one control circuit, there may be two control circuits in the embodiment of the disclosure, which respectively are a first control circuit 3 and a second control circuit 3′. A control signal terminal VDD includes a first control signal terminal VDD1 and a second control signal terminal VDD2 which are electrically connected to the first control circuit 3 and the second control circuit 3′ respectively, and the first control signal terminal VDD1 and the second control signal terminal VDD2 alternately input valid control signals.

The input circuit 1 is configured to control a potential of a first node PU in response to a signal input by the input signal terminal IN.

The reset circuit 2 is configured to provide a signal input by a first reference signal terminal VSS1 to the first node PU in response to a signal input by the reset signal terminal RS.

The first control circuit 3 is configured to provide the signal of the first reference signal terminal VSS1 to a second node PD1 in response to the signal input by the input signal terminal IN, control the potentials of the first node PU and the second node PD1 in response to a signal input by the first control signal terminal VDD1, provide a signal of a second reference signal terminal VSS2 to the gate signal output terminal G-O in response to the potential of the second node PD1, and provide the signal of the first reference signal terminal VSS1 to the output control terminal OC in response to the potential of the second node PD1.

The second control circuit 3′ is configured to provide the signal of the first reference signal terminal VSS1 to a third node PD2 in response to the signal input by the input signal terminal IN, control the potentials of the first node PU and the third node PD2 in response to a signal input by the second control signal terminal VDD2, provide a signal of a second reference signal terminal VSS2 to the gate signal output terminal G-O in response to the potential of the third node PD2, and provide the signal of the first reference signal terminal VSS1 to the output control terminal OC in response to the potential of the third node PD2.

The first output circuit 4 is configured to provide a signal of the clock signal terminal CLK to the gate signal output terminal G-O in response to the potential of the first node PU.

The second output circuit 5 is configured to provide the signal of the clock signal terminal CLK to the output control terminal OC in response to the potential of the first node PU.

The frame start circuit 6 is configured to provide the signal of the first reference signal terminal VSS1 to the first node PU in response to a potential of a signal input by a frame start signal terminal STVO.

Specifically, after each frame image is output, that is, after the plurality of cascaded shift registers provided by the embodiment of the disclosure output signals, before the next frame image is output, the potentials of all first nodes PU in the plurality of cascaded shift registers are reset through the frame start circuit 6.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the input circuit 1 may specifically include a first switching transistor M1; where a gate and a first electrode of the first switching transistor M1 are electrically connected to the input signal terminal, and a second electrode is electrically connected to the first node.

The above is only an example to illustrate the specific structure of the input circuit in the shift register. In the specific implementation, the specific structure of the input circuit is not limited to the above structure provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the reset circuit 2 may include: a second switching transistor M2; and

a gate of the second switching transistor M2 is electrically connected to the reset signal terminal RS, a first electrode is electrically connected to the first node PU, and a second electrode is electrically connected to the first reference signal terminal VSS1.

The above is only an example to illustrate the specific structure of the reset circuit in the shift register. In the specific implementation, the specific structure of the reset circuit is not limited to the above structure provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the first control circuit 3 may include: a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9 and a tenth switching transistor M10.

A gate of the third switching transistor M3 is electrically connected to the input signal terminal IN, a first electrode of the third switching transistor M3 is electrically connected to the second node PDT, and a second electrode of third switching transistor M3 is electrically connected to the first reference signal terminal VSS1.

A gate of the fourth switching transistor M4 is electrically connected to the second node PD1, a first electrode of the fourth switching transistor M4 is electrically connected to the first node PU, and a second electrode of the fourth switching transistor M4 is electrically connected to the first reference signal terminal VSS1.

A gate of the fifth switching transistor M5 is electrically connected to the second node PD1, a first electrode of the fifth switching transistor M4 is electrically connected to the gate signal output terminal G-O of the gate driving circuit, and a second electrode of the fifth switching transistor M4 is electrically connected to the second reference signal terminal VSS2.

Agate and a first electrode of the sixth switching transistor M6 are electrically connected to the first control signal terminal VDD1, and a second electrode of the sixth switching transistor M6 is electrically connected to a first electrode of the eighth switching transistor M8 and a gate of the seventh switching transistor M7 respectively.

A first electrode of the seventh switching transistor M7 is electrically connected to the first control signal terminal VDD1, and a second electrode of the seventh switching transistor M7 is electrically connected to the second node PD1.

Agate of the eighth switching transistor M8 is electrically connected to the first node PU, and a second electrode of the eighth switching transistor M8 is electrically connected to the first reference signal terminal VSS1.

A gate of the ninth switching transistor M9 is electrically connected to the first node PU, a first electrode of the ninth switching transistor M9 is electrically connected to the second node PD1, and a second electrode of the ninth switching transistor M9 is electrically connected to the first reference signal terminal VSS1.

Agate of the tenth switching transistor M10 is electrically connected to the second node PD1, a first electrode of the tenth switching transistor M10 is electrically connected to the output control terminal OC of the gate driving circuit, and a second electrode of the tenth switching transistor M10 is electrically connected to the first reference signal terminal VSS1.

The second control circuit 3′ may include: a fourteenth switching transistor M3′, a fifteenth switching transistor M4′, a sixteenth switching transistor M5′, a seventeenth switching transistor M6′, an eighteenth switching transistor M7′, a nineteenth switching transistor M8′, a twentieth switching transistor M9′ and a twenty-first switching transistor M10′.

A gate of the fourteenth switching transistor M3′ is electrically connected to the input signal terminal IN, a first electrode of the fourteenth switching transistor M3′ is electrically connected to the second node PD1, and a second electrode of the fourteenth switching transistor M3′ is electrically connected to the first reference signal terminal VSS1.

Agate of the fifteenth switching transistor M4′ is electrically connected to the third node PD2, a first electrode of the fifteenth switching transistor M4′ is electrically connected to the first node PU, and a second electrode of the fifteenth switching transistor M4′ is electrically connected to the first reference signal terminal VSS1.

Agate of the sixteenth switching transistor M5′ is electrically connected to the third node PD2, a first electrode of the sixteenth switching transistor M5′ is electrically connected to the gate signal output terminal G-O of the gate driving circuit, and a second electrode of the sixteenth switching transistor M5′ is electrically connected to the second reference signal terminal VSS2.

A gate and a first electrode of the seventeenth switching transistor M6′ are electrically connected to the second control signal terminal VDD2, and a second electrode of the seventeenth switching transistor M6′ is electrically connected to a first electrode of the nineteenth switching transistor M8′ and a gate of the eighteenth switching transistor M7′ respectively.

A first electrode of the eighteenth switching transistor M7′ is electrically connected to the second control signal terminal VDD2, and a second electrode of the eighteenth switching transistor M7′ is electrically connected to the third node PD2.

A gate of the nineteenth switching transistor M8′ is electrically connected to the first node PU, and a second electrode of the nineteenth switching transistor M8′ is electrically connected to the first reference signal terminal VSS1.

Agate of the twentieth switching transistor M9′ is electrically connected to the first node PU, a first electrode of the twentieth switching transistor M9′ is electrically connected to the third node PD2, and a second electrode of the twentieth switching transistor M9′ is electrically connected to the first reference signal terminal VSS1.

Agate of the twenty-first switching transistor M10′ is electrically connected to the third node PD2, a first electrode of the twenty-first switching transistor M10′ is electrically connected to the output control terminal OC of the gate driving circuit, and a second electrode of the twenty-first switching transistor M10′ is electrically connected to the first reference signal terminal VSS1.

The above is only an example to illustrate the specific structures of the first control circuit and the second control circuit in the shift register. In the specific implementation, the specific structures of the first control circuit and the second control circuit are not limited to the above structures provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the first output circuit 4 may specifically include an eleventh switching transistor M11 and a capacitor C.

Agate of the eleventh switching transistor M11 is electrically connected to the first node PU, a first electrode of the eleventh switching transistor M11 is electrically connected to the clock signal terminal CLK, and a second electrode of the eleventh switching transistor M11 is electrically connected to the gate signal output terminal G-O of the gate driving circuit.

The capacitor C is connected between the gate and the second electrode of the eleventh switching transistor M11.

The above is only an example to illustrate the specific structure of the first output circuit in the shift register. In the specific implementation, the specific structure of the first output circuit is not limited to the above structure provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the second output circuit 5 may specifically include: a twelfth switching transistor M12; and

a gate of the twelfth switching transistor M12 is electrically connected to the first node PU, a first electrode of the twelfth switching transistor M12 is electrically connected to the clock signal terminal CLK, and a second electrode of the twelfth switching transistor M12 is electrically connected to the output control terminal OC of the gate driving circuit.

The above is only an example to illustrate the specific structure of the second output circuit in the shift register. In the specific implementation, the specific structure of the second output circuit is not limited to the above structure provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , the frame start circuit 6 may specifically include: a thirteenth switching transistor M13; and

a gate of the thirteenth switching transistor M13 is electrically connected to the frame start signal terminal STVO, a first electrode of the thirteenth switching transistor M13 is electrically connected to the first node PU, and a second electrode of the thirteenth switching transistor M13 is electrically connected to the first reference signal terminal VSS1.

The above is only an example to illustrate the specific structure of the frame start circuit in the shift register. In the specific implementation, the specific structure of the frame start circuit is not limited to the above structure provided by the embodiment of the disclosure, and may also be other structures known to those skilled in the art, which is not limited here.

It should be noted that in a normal shift register, a signal output by the gate signal output terminal G-O of this stage is used as a signal of the input signal terminal IN of the gate driving circuit of next stage, however, in the specific working process, the signal output by the gate signal output terminal G-O may fluctuate due to the influence of a gate line, resulting in unstable output. Therefore, a signal output by the second output circuit in the Nth shift register of the disclosure is output from the output control terminal OC to be used as a signal of the input signal terminal IN of a (N+4)th shift register, which can improve the stability of signal output and ensure the normal output of the gate driving circuit.

It should be noted that the embodiment of the disclosure mainly solves the problem that in an existing 75-inch/8K/120 Hz display product, there are many cascade signal lines for cascading the shift registers, and the flexibility of the external circuit board to provide clock signals to the existing gate driving circuit is poor, the input and output working principle of the gate driving circuit in a normal working state is the same as the working principle of the gate driving circuit in the related art, which will be not described in detail here.

In the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, as shown in FIG. 5 , all switching transistors may be N-type transistors. Potentials of the first reference signal terminal VSS1 and the second reference signal terminal VSS2 are both low potentials, the first control signal terminal VDD1 and the second control signal terminal VDD2 alternately output high and low potentials, that is, when the first control signal terminal VDD1 is at a high potential, the second control signal terminal VDD2 is at a low potential, and when the first control signal terminal VDD1 is at the low potential, the second control signal terminal VDD2 is at the high potential.

Of course, in the specific implementation, in the gate driving circuit provided by the embodiment of the disclosure, all switching transistors may also be P-type transistors.

Moreover, in the specific implementation, the N-type transistors are turned on in response to the high potential, and are turned off in response to the low potential; and the P-type transistors are turned off in response to the high potential, and are turned on in response to the low potential.

It should be noted that the switching transistors mentioned in the above embodiments of the disclosure may be thin film transistors (TFTs), and may also be metal oxide semiconductors (MOSs), which is not limited here. In the specific implementation, the functions of the first electrodes and the second electrodes of these switching transistors may be interchanged according to the type of the transistor and the input signals, which is not specifically distinguished. Specifically, the first electrodes of the switching transistors mentioned in the above embodiments of the disclosure may be sources, and the second electrodes may be drains; or the first electrodes may be drains, and the second electrodes may be sources, which is not specifically distinguished.

Based on the same inventive concept, an embodiment of the disclosure further provides a display device, including the above gate driving circuit. The display device may be any display panels of products with display functions such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The implementation of the display device may refer to the implementation of the above gate driving circuit, and the repetition will not be made.

The embodiments of the disclosure provide the gate driving circuit and the display device. According to the gate driving circuit, in every five adjacent shift registers, the output control terminal of the first shift register is electrically connected to the input signal terminal of the fifth shift register; and in every six adjacent shift registers, the output control terminal of the sixth shift register is electrically connected to the reset signal terminal of the first shift register. In the gate driving circuit of the cascade structure provided by the disclosure, there are fewer cascade signal lines, thereby saving space, further implementing the narrow bezel of the display device; in addition, for the gate driving circuit of the cascade structure provided by the disclosure, the signal provided by the external circuit board can be more flexible, even if a display product is manufactured, the pulse width of the clock signal can be adjusted by means of the external circuit board, thereby adjusting the high-level width of the gate signal output by the gate signal output terminal, and the flexibility is high.

Obviously, those skilled in the art can make various changes and modifications to the disclosure without departing from the spirit and scope of the disclosure. As such, provided that these modifications and variations of the disclosure fall within the scope of the claims of the disclosure and their equivalents, the disclosure is also intended to cover such modifications and variations. 

1-12. (canceled)
 13. A gate driving circuit, comprising a plurality of cascaded shift registers, wherein each shift register comprises an input signal terminal, a reset signal terminal, an output control terminal and a gate signal output terminal; gate signal output terminals are electrically connected to gate lines of a display panel in a one-to-one corresponding mode; in every five adjacent shift registers, an output control terminal of a first shift register among the every five adjacent shift registers is electrically connected to an input signal terminal of a fifth shift register among the every five adjacent shift registers; and in every six adjacent shift registers, an output control terminal of a sixth shift register among the every six adjacent shift registers is electrically connected to the reset signal terminal of the first shift register among the every six adjacent shift registers.
 14. The gate driving circuit according to claim 13, comprising 10 clock signal lines, wherein each shift register further comprises a clock signal terminal; a clock signal terminal of a (10k−9)th shift register is electrically connected to a first clock signal line; a clock signal terminal of a (10k−8)th shift register is electrically connected to a second clock signal line; a clock signal terminal of a (10k−7)th shift register is electrically connected to a third clock signal line; a clock signal terminal of a (10k−6)th shift register is electrically connected to a fourth clock signal line; a clock signal terminal of a (10k−5)th shift register is electrically connected to a fifth clock signal line; a clock signal terminal of a (10k−4)th shift register is electrically connected to a sixth clock signal line; a clock signal terminal of a (10k−3)th shift register is electrically connected to a seventh clock signal line; a clock signal terminal of a (10k−2)th shift register is electrically connected to an eighth clock signal line; a clock signal terminal of a (10k−1)th shift register is electrically connected to a ninth clock signal line; and a clock signal terminal of a (10k)th shift register is electrically connected to a tenth clock signal line; and k is a positive integer.
 15. The gate driving circuit according to claim 14, wherein a clock signal duty cycle of each clock signal line is approximately 40%.
 16. The gate driving circuit according to claim 13, wherein each shift register comprises: an input circuit, a reset circuit, a control circuit, a first output circuit, a second output circuit and a frame start circuit; wherein the input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal; the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal; the control circuit is configured to provide the signal of the first reference signal terminal to a second node in response to the signal input by the input signal terminal, control the potentials of the first node and the second node in response to a signal input by a control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the second node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the second node; the first output circuit is configured to provide a signal of the clock signal terminal to the gate signal output terminal in response to the potential of the first node; the second output circuit is configured to provide the signal of the clock signal terminal to the output control terminal in response to the potential of the first node; and the frame start circuit is configured to provide the signal of the first reference signal terminal to the first node in response to a signal input by a frame start signal terminal.
 17. The gate driving circuit according to claim 16, wherein the input circuit comprises: a first switching transistor; and a gate and a first electrode of the first switching transistor are electrically connected to the input signal terminal, and a second electrode of the first switching transistor is electrically connected to the first node.
 18. The gate driving circuit according to claim 16, wherein the reset circuit comprises: a second switching transistor; and a gate of the second switching transistor is electrically connected to the reset signal terminal, a first electrode of the second switching transistor is electrically connected to the first node, and a second electrode of the second switching transistor is electrically connected to the first reference signal terminal.
 19. The gate driving circuit according to claim 16, wherein the control circuit comprises: a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor and a tenth switching transistor; a gate of the third switching transistor is electrically connected to the input signal terminal, a first electrode of the third switching transistor is electrically connected to the second node, and a second electrode of the third switching transistor is electrically connected to the first reference signal terminal; a gate of the fourth switching transistor is electrically connected to the second node, a first electrode of the fourth switching transistor is electrically connected to the first node, and a second electrode of the fourth switching transistor is electrically connected to the first reference signal terminal; a gate of the fifth switching transistor is electrically connected to the second node, a first electrode of the fifth switching transistor is electrically connected to the gate signal output terminal, and a second electrode of the fifth switching transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the sixth switching transistor are electrically connected to the control signal terminal, and a second electrode of the sixth switching transistor is electrically connected to a first electrode of the eighth switching transistor and a gate of the seventh switching transistor respectively; a first electrode of the seventh switching transistor is electrically connected to the control signal terminal, and a second electrode of the seventh switching transistor is electrically connected to the second node; a gate of the eighth switching transistor is electrically connected to the first node, and a second electrode of the eighth switching transistor is electrically connected to the first reference signal terminal; a gate of the ninth switching transistor is electrically connected to the first node, a first electrode of the ninth switching transistor is electrically connected to the second node, and a second electrode of the ninth switching transistor is electrically connected to the first reference signal terminal; and a gate of the tenth switching transistor is electrically connected to the second node, a first electrode of the tenth switching transistor is electrically connected to the output control terminal, and a second electrode of the tenth switching transistor is electrically connected to the first reference signal terminal.
 20. The gate driving circuit according to claim 19, wherein two said control circuits are provided and electrically connected to different control signal terminals respectively, and the two control signal terminals alternately input valid control signals.
 21. The gate driving circuit according to claim 16, wherein the first output circuit comprises: an eleventh switching transistor and a capacitor; a gate of the eleventh switching transistor is electrically connected to the first node, a first electrode of the eleventh switching transistor is electrically connected to the clock signal terminal, and a second electrode of the eleventh switching transistor is electrically connected to the gate signal output terminal; and the capacitor is connected between the gate and the second electrode of the eleventh switching transistor.
 22. The gate driving circuit according to claim 19, wherein the second output circuit comprises: a twelfth switching transistor; and a gate of the twelfth switching transistor is electrically connected to the first node, a first electrode of the twelfth switching transistor is electrically connected to the clock signal terminal, and a second electrode of the twelfth switching transistor is electrically connected to the output control terminal.
 23. The gate driving circuit according to claim 16, wherein the frame start circuit comprises: a thirteenth switching transistor; and a gate of the thirteenth switching transistor is electrically connected to the frame start signal terminal, a first electrode of the thirteenth switching transistor is electrically connected to the first node, and a second electrode of the thirteenth switching transistor is electrically connected to the first reference signal terminal.
 24. A display device, comprising a gate driving circuit, wherein the gate driving circuit comprises: each shift register comprises an input signal terminal, a reset signal terminal, an output control terminal and a gate signal output terminal; gate signal output terminals are electrically connected to gate lines of a display panel in a one-to-one corresponding mode; in every five adjacent shift registers, an output control terminal of a first shift register among the every five adjacent shift registers is electrically connected to an input signal terminal of a fifth shift register among the every five adjacent shift registers; and in every six adjacent shift registers, an output control terminal of a sixth shift register among the every six adjacent shift registers is electrically connected to the reset signal terminal of the first shift register among the every six adjacent shift registers.
 25. The display device according to claim 24, wherein the gate driving circuit comprises 10 clock signal lines, wherein each shift register further comprises a clock signal terminal; a clock signal terminal of a (10k−9)th shift register is electrically connected to a first clock signal line; a clock signal terminal of a (10k−8)th shift register is electrically connected to a second clock signal line; a clock signal terminal of a (10k−7)th shift register is electrically connected to a third clock signal line; a clock signal terminal of a (10k−6)th shift register is electrically connected to a fourth clock signal line; a clock signal terminal of a (10k−5)th shift register is electrically connected to a fifth clock signal line; a clock signal terminal of a (10k−4)th shift register is electrically connected to a sixth clock signal line; a clock signal terminal of a (10k−3)th shift register is electrically connected to a seventh clock signal line; a clock signal terminal of a (10k−2)th shift register is electrically connected to an eighth clock signal line; a clock signal terminal of a (10k−1)th shift register is electrically connected to a ninth clock signal line; and a clock signal terminal of a (10k)th shift register is electrically connected to a tenth clock signal line; and k is a positive integer.
 26. The display device according to claim 24, wherein each shift register comprises: an input circuit, a reset circuit, a control circuit, a first output circuit, a second output circuit and a frame start circuit; wherein the input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal; the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal; the control circuit is configured to provide the signal of the first reference signal terminal to a second node in response to the signal input by the input signal terminal, control the potentials of the first node and the second node in response to a signal input by a control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the second node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the second node; the first output circuit is configured to provide a signal of the clock signal terminal to the gate signal output terminal in response to the potential of the first node; the second output circuit is configured to provide the signal of the clock signal terminal to the output control terminal in response to the potential of the first node; and the frame start circuit is configured to provide the signal of the first reference signal terminal to the first node in response to a signal input by a frame start signal terminal.
 27. The display device according to claim 26, wherein the input circuit comprises: a first switching transistor; and a gate and a first electrode of the first switching transistor are electrically connected to the input signal terminal, and a second electrode of the first switching transistor is electrically connected to the first node.
 28. The display device according to claim 26, wherein the reset circuit comprises: a second switching transistor; and a gate of the second switching transistor is electrically connected to the reset signal terminal, a first electrode of the second switching transistor is electrically connected to the first node, and a second electrode of the second switching transistor is electrically connected to the first reference signal terminal.
 29. The display device according to claim 26, wherein the control circuit comprises: a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor and a tenth switching transistor; a gate of the third switching transistor is electrically connected to the input signal terminal, a first electrode of the third switching transistor is electrically connected to the second node, and a second electrode of the third switching transistor is electrically connected to the first reference signal terminal; a gate of the fourth switching transistor is electrically connected to the second node, a first electrode of the fourth switching transistor is electrically connected to the first node, and a second electrode of the fourth switching transistor is electrically connected to the first reference signal terminal; a gate of the fifth switching transistor is electrically connected to the second node, a first electrode of the fifth switching transistor is electrically connected to the gate signal output terminal, and a second electrode of the fifth switching transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the sixth switching transistor are electrically connected to the control signal terminal, and a second electrode of the sixth switching transistor is electrically connected to a first electrode of the eighth switching transistor and a gate of the seventh switching transistor respectively; a first electrode of the seventh switching transistor is electrically connected to the control signal terminal, and a second electrode of the seventh switching transistor is electrically connected to the second node; a gate of the eighth switching transistor is electrically connected to the first node, and a second electrode of the eighth switching transistor is electrically connected to the first reference signal terminal; a gate of the ninth switching transistor is electrically connected to the first node, a first electrode of the ninth switching transistor is electrically connected to the second node, and a second electrode of the ninth switching transistor is electrically connected to the first reference signal terminal; and a gate of the tenth switching transistor is electrically connected to the second node, a first electrode of the tenth switching transistor is electrically connected to the output control terminal, and a second electrode of the tenth switching transistor is electrically connected to the first reference signal terminal.
 30. The display device according to claim 26, wherein the first output circuit comprises: an eleventh switching transistor and a capacitor; a gate of the eleventh switching transistor is electrically connected to the first node, a first electrode of the eleventh switching transistor is electrically connected to the clock signal terminal, and a second electrode of the eleventh switching transistor is electrically connected to the gate signal output terminal; and the capacitor is connected between the gate and the second electrode of the eleventh switching transistor.
 31. The gate driving circuit according to claim 13, wherein each shift register comprises: an input circuit, a reset circuit, a first control circuit, a second control circuit, a first output circuit, a second output circuit and a frame start circuit; wherein the input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal; the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal; the first control circuit is configured to provide the signal of the first reference signal terminal to a second node in response to the signal input by the input signal terminal, control the potentials of the first node and the second node in response to a signal input by a first control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the second node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the second node; the second control circuit is configured to provide the signal of the first reference signal terminal to a third node in response to the signal input by the input signal terminal, control the potentials of the first node and the third node in response to a signal input by a second control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the third node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the third node; the first output circuit is configured to provide a signal of the clock signal terminal to the gate signal output terminal in response to the potential of the first node; the second output circuit is configured to provide the signal of the clock signal terminal to the output control terminal in response to the potential of the first node; and the frame start circuit is configured to provide the signal of the first reference signal terminal to the first node in response to a signal input by a frame start signal terminal.
 32. The gate driving circuit according to claim 31, wherein the first control circuit comprises: a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor and a tenth switching transistor; a gate of the third switching transistor is electrically connected to the input signal terminal, a first electrode of the third switching transistor is electrically connected to the second node, and a second electrode of the third switching transistor is electrically connected to the first reference signal terminal; a gate of the fourth switching transistor is electrically connected to the second node, a first electrode of the fourth switching transistor is electrically connected to the first node, and a second electrode of the fourth switching transistor is electrically connected to the first reference signal terminal; a gate of the fifth switching transistor is electrically connected to the second node, a first electrode of the fifth switching transistor is electrically connected to the gate signal output terminal, and a second electrode of the fifth switching transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the sixth switching transistor are electrically connected to the first control signal terminal, and a second electrode of the sixth switching transistor is electrically connected to a first electrode of the eighth switching transistor and a gate of the seventh switching transistor respectively; a first electrode of the seventh switching transistor is electrically connected to the first control signal terminal, and a second electrode of the seventh switching transistor is electrically connected to the second node; a gate of the eighth switching transistor is electrically connected to the first node, and a second electrode of the eighth switching transistor is electrically connected to the first reference signal terminal; a gate of the ninth switching transistor is electrically connected to the first node, a first electrode of the ninth switching transistor is electrically connected to the second node, and a second electrode of the ninth switching transistor is electrically connected to the first reference signal terminal; and a gate of the tenth switching transistor is electrically connected to the second node, a first electrode of the tenth switching transistor is electrically connected to the output control terminal, and a second electrode of the tenth switching transistor is electrically connected to the first reference signal terminal; the second control circuit comprises: a fourteenth switching transistor, a fifteenth switching transistor, a sixteenth switching transistor, a seventeenth switching transistor, an eighteenth switching transistor, a nineteenth switching transistor, a twentieth switching transistor and a twenty-first switching transistor; wherein a gate of the fourteenth switching transistor is electrically connected to the input signal terminal, a first electrode of the fourteenth switching transistor is electrically connected to the second node, and a second electrode of the fourteenth switching transistor is electrically connected to the first reference signal terminal; a gate of the fifteenth switching transistor is electrically connected to the third node, a first electrode of the fifteenth switching transistor is electrically connected to the first node, and a second electrode of the fifteenth switching transistor is electrically connected to the first reference signal terminal; a gate of the sixteenth switching transistor is electrically connected to the third node, a first electrode of the sixteenth switching transistor is electrically connected to the gate signal output terminal of the gate driving circuit, and a second electrode of the sixteenth switching transistor is electrically connected to the second reference signal terminal; a gate and a first electrode of the seventeenth switching transistor are electrically connected to the second control signal terminal, and a second electrode of the seventeenth switching transistor is electrically connected to a first electrode of the nineteenth switching transistor and a gate of the eighteenth switching transistor respectively; a first electrode of the eighteenth switching transistor is electrically connected to the second control signal terminal, and a second electrode of the eighteenth switching transistor is electrically connected to the third node; a gate of the nineteenth switching transistor is electrically connected to the first node, and a second electrode of the nineteenth switching transistor is electrically connected to the first reference signal terminal; a gate of the twentieth switching transistor is electrically connected to the first node, a first electrode of the twentieth switching transistor is electrically connected to the third node, and a second electrode of the twentieth switching transistor is electrically connected to the first reference signal terminal; and a gate of the twenty-first switching transistor is electrically connected to the third node, a first electrode of the twenty-first switching transistor is electrically connected to the output control terminal of the gate driving circuit, and a second electrode of the twenty-first switching transistor is electrically connected to the first reference signal terminal. 